fn7376 rev 2.00 page 1 of 8 january 31, 2005 fn7376 rev 2.00 january 31, 2005 el5001 6-channel clock driver datasheet the el5001 is a 6-c hannel level shifting driver designed primarily for use as a clock driver in ltps lcd displays. the el5001 buffers and level shifts si x logic level in put signals. the six channels are grouped in to two sets, one of two channels and one of four ch annels. each set can be configured in the inverting or non-inverting modes. operating from 3.3v input logic, the output swing is set using two reference input pins. these pins can be up to 18v differential and are not buffe red, so should therefore be bypassed effectively. the el5001 is designed to dri ve capacitive loads of 500pf with rise and fall ti mes of just 20ns. a three-state pin is provided to set all outputs in to a high impedance mode. the enable pin can be u sed to put t he device in to a power save mode where the power consumption drops to just 3a. the el5001 is a vailable in 20-pin qfn (4mm x 4mm) and htssop packages. both are sp ecified for operation over the -40c to +85c temperature range. features ? six inverting/non-inverting channels ? 3.3v input logic ? 18v output ? 250a typical supply current ? drives up to 500pf ?t r /t f = 35ns max ? disable function ? 20-pin qfn (4mm x 4mm) and htssop packages ? pb-free available (rohs compliant) applications ? ltps lcd clock drivers ? ccd driving ? level shifters ordering information part number package tape & reel pkg. dwg. # part number package tape & reel pkg. dwg. # el5001il 20-pin qfn (4mm x 4mm) - mdp0046 el5001ire 20-pin htssop - mdp0048 el5001il-t7 20-pin qfn (4mm x 4mm) 7 mdp0046 el5001ire-t7 20-pin htssop 7 mdp0048 el5001il-t13 20-pin qfn (4mm x 4mm) 13 mdp0046 EL5001IRE-T13 20-pin htssop 13 mdp0048 el5001ilz (see note) 20-pin qfn (4mm x 4mm) (pb-free) - mdp0046 el5001irez (see note) 20-pin htssop (pb-free) - mdp0048 el5001ilz-t7 (see note) 20-pin qfn (4mm x 4mm) (pb-free) 7 mdp0046 el5001irez-t7 (see note) 20-pin htssop (pb-free) 7 mdp0048 el5001ilz-t13 (see note) 20-pin qfn (4mm x 4mm) (pb-free) 13 mdp0046 el5001irez-t13 (see note) 20-pin htssop (pb-free) 13 mdp0048 note: intersil pb-free products employ special pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are rohs compliant and compatible with both snpb and pb-free soldering operations. intersil pb-free products are msl classified at pb- free peak reflow temperatures that meet or exceed the pb-free r equirements of ipc/jedec j std-020c. n o t r e c o m m e n d e d f o r n e w d e s i g n s n o r e c o m m e n d e d r e p l a c e m e n t c o n t a c t o u r t e c h n i c a l s u p p o r t c e n t e r a t 1 - 8 8 8 - i n t e rs i l o r w w w . in t e r s i l . c o m / t s c
el5001 fn7376 rev 2.00 page 2 of 8 january 31, 2005 pinouts el5001 [20-pin qfn (4mm x 4mm)] top view el5001 (20-pin hssop) top view 1 2 3 4 15 14 13 12 6 7 8 9 20 19 18 17 in1 in2 in3 in4 in6 inv1 inv2 vl en tri gnd vh out1 out2 out3 out4 thermal pad 5 in5 10 out6 11 out5 16 nc 1 2 3 4 16 15 14 13 5 6 7 12 11 9 8 10 20 19 18 17 tri en in1 in2 in3 in4 in5 in6 inv1 inv2 gnd vh out1 out2 out3 out4 out5 out6 vl nc thermal pad
el5001 fn7376 rev 2.00 page 3 of 8 january 31, 2005 absolute maximum ratings (t a = 25c) supply voltage between v sd and gnd . . . . . . . . . . . . . . . . . . .18v maximum continuous output current . . . . . . . . . . . . . . . . . . . 50ma ambient operating temperature . . . . . . . . . . . . . . . .-4 0c to +85c maximum die temperature . . . . . . . . . . . . . . . . . . . . . . . . . . +125c storage temperature . . . . . . . . . . . . . . . . . . . . . . . .-65c to +150c power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see curves caution: stresses above those listed in ?absolute maximum ratings? may cause permanent damage to the device. this is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. important note: all parameters having min/max specifications are guaranteed. typical values are for information purposes only. u nless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: t j = t c = t a electrical specifications v h = 10v, v l = -5v, en = 3v, unless otherwise specified . parameter description condition min typ max unit power supply i s supply current en = 3v, in x = 0v 750 1200 a en = 3v, in x = 3v 250 500 a i s_dis supply current - disabled en = 0v, in x = 0v 3 a v lr v l range -13 0 v v hr v h range 518v v h -v l maximum v h - v l range 0 18 v input v ih logic 1 input voltage 2.0 v i ih logic 1 input current 0.1 10 a v il logic 0 input voltage 0.8 v i il logic 0 input current 0.1 10 a c in input capacitance 3.5 pf r in input resistance 50 m ? output v oh v outl high in x = 10v, i l = 10ma 9.80 9.88 v v ol v outl low in x = 0v, i l = -10ma -4.90 -4.88 v r oh on resistance v h to out i l = 50ma 11 15 ? r ol on resistance v l to out i l = 50ma 11 15 ? i peak peak output current 500 ma i l out leakage current 0.1 0.5 a switching characteristics t r rise time c l = 500pf 20 35 ns t f fall time c l = 500pf 20 35 ns t rfd t r , t f matching c l = 500pf 5 ns t d + turn on delay c l = 500pf 55 ns t d - turn off delay c l = 500pf 55 ns t dd t d +, t d -, matching c l = 500pf 5 ns t en enable time 9.8 s t dis disable time 2.2 s
el5001 fn7376 rev 2.00 page 4 of 8 january 31, 2005 typical performance curves figure 1. rise time output 6v p-p figure 2. fall time output 6v p-p figure 3. rise time output 12v p-p figure 4. fall time output 12v p-p figure 5. rise time output 5v p-p figure 6. fall time output 5v p-p time (40ns/div) voltage (1v/div) r l =0 ? c l =500pf v s =v-=0v v s =v+=18v rise time ? t=37.55ns time (40ns/div) voltage (1v/div) r l =0 ? c l =500pf v s =v-=0v v s =v+=18v fall time ? t=29ns time (20ns/div) voltage (2v/div) r l =0 ? c l =500pf v s =v-=0v v s =v+=18v rise time ? t=23.63ns time (20ns/div) voltage (2v/div) r l =0 ? c l =500pf v s =v-=0v v s =v+=18v fall time ? t=22.93ns time (20ns/div) voltage (2v/div) r l =0 ? c l =500pf v s =v-=0v v s =v+=18v rise time ? t=40.08ns time (20ns/div) voltage (2v/div) r l =0 ? c l =500pf v s =v-=0v v s =v+=18v fall time ? t=30.57ns
el5001 fn7376 rev 2.00 page 5 of 8 january 31, 2005 figure 7. disable response figure 8. enable response figure 9. turn-off (tri) figure 10. turn-on (tri) figure 11. enable/disable threshold figure 12. propagation delay typical performance curves (continued) time (10s/div) voltage (1v/div) r l =0 ? c l =500pf v s =v-=0v v s =v+=18v disable ? t=2.2s ch2 ch3 r l =0 ? c l =500pf v s =v-=0v v s =v+=18v enable ? t=9.8s ch2 ch3 time (10s/div) voltage (1v/div) turn-off ? t=90ns r l =0 ? c l =500pf v s =v-=0v v s =v+=18v ch2 ch3 time (100ns/div) voltage (ch1-1v/div)(ch2-5v/div) turn-on ? t=90ns r l =0 ? c l =500pf v s =v-=0v v s =v+=18v ch2 ch3 time (100ns/div) voltage (ch1-1v/div)(ch2-5v/div) ground 1.78v 1.32v r l =0 ? c l =500pf v s =v-=0v v s =v+=18v ch2 ch3 time (2s/div) voltage (ch2-5v/div)(ch3-1v/div) propagation delay ? t=52ns r l =0 ? c l =500pf v s =v-=0v v s =v+=18v time (40ns/div) voltage (2v/div)
el5001 fn7376 rev 2.00 page 6 of 8 january 31, 2005 figure 13. skew figure 14. input current vs voltage figure 15. package power dissipation vs ambient temperature figure 16. package power dissipation vs ambient temperature figure 17. package power dissipation vs ambient temperature figure 18. package power dissipation vs ambient temperature typical performance curves (continued) maximum skew=5.0ns r l =0 ? c l =500pf v s =v-=0v v s =v+=18v time (10ns/div) voltage (200mv/div) v in (v) i in (ma) 150 r l =0 ? c l =500pf 100 0 -100 -200 -300 -150 -250 50 -50 -2-1 12345678 0 jedec jesd51-7 high effective thermal conductivity test board - htssop exposed diepad soldered to pcb per jesd51-5 2.857w ambient temperature (c) power dissipation (w) 3.5 3 2 1 0 0.5 2.5 1.5 0 25 75 100 125 85 150 50 ? j a = 3 5 c / w h t s s o p 2 0 jedec jesd51-3 low effective thermal conductivity test board ambient temperature (c) power dissipation (w) 1 0.9 0.5 0.2 0 0.1 0.7 0.3 0 25 75 100 125 85 150 50 0.8 0.4 0.6 800mw ? j a = 1 2 5 c / w h ts s o p 2 0 ambient temperature (c) power dissipation (w) 0.8 0.7 0.3 0 0.1 0.5 0 25 75 100 125 85 150 50 0.6 0.2 0.4 jedec jesd51-3 and se mi g42-88 (single layer) test board 667mw ? j a = 1 5 0 c / w q f n 2 0 ( 4 m m x 4 m m ) jedec jesd51-7 high effective thermal conductivity test board - qfn exposed diepad soldered to pcb per jesd51-5 ambient temperature (c) power dissipation (w) 3 2.5 0.5 0 1.5 0 25 75 100 125 85 150 50 2 1 2.500w ? j a = 4 0 c / w q f n 2 0 ( 4 m m x 4 m m )
el5001 fn7376 rev 2.00 page 7 of 8 january 31, 2005 el5001 test board circuit layout block diagram 1 2 3 4 16 15 14 13 5 6 7 12 11 9 8 10 20 19 18 17 tri en in1 in2 in3 in4 in5 in6 inv1 inv2 gnd vh out1 out2 out3 out4 out5 out6 vl nc + + tri en in1 in2 in3 in4 in5 in6 inv1 inv2 r 10 open r 9 50 ? r 8 50 ? r 7 50 ? 50 ? r 6 50 ? r 5 50 ? r 4 50 ? r 3 50 ? r 2 open r 1 50 ? c 2 33nf r 11 3.3 ? c 3 4.7f l 1 ferrite bead d 1 mbrm120lt3 v s + out1 out2 out3 out4 out5 out6 c 7 500pf c 8 500pf c 9 500pf c 10 500pf c 11 500pf c 12 500pf l 2 ferrite bead c 5 33nf r 12 3.3 ? c 6 4.7f d 2 mbrm120lt3 v s - gnd level shifter 3-state control v s + v s - input gnd oe v h output v l
fn7376 rev 2.00 page 8 of 8 january 31, 2005 el5001 intersil products are manufactured, assembled and tested utilizing iso9001 quality systems as noted in the quality certifications found at www.intersil.com/en/suppor t/qualandreliability.html intersil products are sold by description on ly. intersil may modify the circuit design an d/or specifications of products at any time without notice, provided that such modification does not, in intersil's sole judgment, affect the form, fit or function of the product. accordingly, the reader is cautioned to verify that datasheets are current before placing orders. information fu rnished by intersil is believed to be accu rate and reliable. however, no responsib ility is assumed by intersil or its subsidiaries for its use; nor for any infrin gements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com for additional products, see www.intersil.com/en/products.html ? copyright intersil americas ll c 2004-2005. all rights reserved. all trademarks and registered trademarks are the property of their respective owners. applications information the el5001, a six channel h igh performance buffer, is directed primarily as a clo ck driver to lpts lcd display applications. the six input c hannels are grouped into one group of four inputs and one group of two inputs each with a single pin (inv1 or inv2) to toggle the polarity from inverting to non-inverting. each chann el consists of a single n- channel low side driver and s ingle p-channel high side driver. these 11 ? devices pull the output t o either the high or low voltage on v h and v l respectively, depending on the logic input signal. a common 3-state pin is availa ble that when activated will pull all 6-channel outputs to t he high impedance state. enable and disable pins t urn shutdown both inputs and outputs. timing plots for 3- state, enable, and disable functions are included in the characterization documentation. the el5001 is available in eit her a 20-pin h tssop or qfn (4mm x 4mm) packages to provide a choice for power dissipation considerations. supply voltage and input compatibility the el5001 is design ed to operate at a maximum potential range from 0v to 18v. because the el5001 does not contain a true analog switch, the positive suppl y must always be 4v higher than the negative supply. all input pins are compati ble with both 3v and 5v cmos signals. with the positive supply set to v s = 5v the el5001 is compatible with ttl inputs. power supply bypassing due to the high switching currents generated by the el5001 power supply bypassing is v ery important on both the positive and negative supplies. a 4.7f tantalum capacitor can be used in parallel with a 0 .1f low-inductance ceramic mlc capacitor. as with all bypass components, these should be placed as close as possible to the supply pins. we also recommend the v l and v h pins have som e level of bypassing especially when the device is driving highly capacitive loads. power dissipation calculation when switching at high speeds, or driving heavy loads, the el5001 drive capability is limited by the rise in die temperature brought about by internal power dissipation. for reliable operation die temper ature must be kept below t jmax (125c). it is necessary t o calculate the power dissipation for a given applicat ion prior to selecting package type. power dissipation may be calculated: where: v s = total power supply t o the el50 01 (from v s + to v s -) v out = swing on the output (v h - v l ) c l = load capacitance c int = internal load capacitance (80pf max) i s = quiescent supply current (3ma max) f = frequency having obtained the applicatio n's power dissipation, the maximum junction temperature can be calculated: where: t jmax = maximum junction temperature (125c) t max = maximum ambient operating temperature pd = power dissipation calculated above ? ja = thermal resistance, junction to ambient, of the application (package + pcb combination) pd v s ? i s ? 4 ? 1 + ? c int ? v s 2 f ? c l ? v out 2 f ? ? ? + ? ? ? = ? ja pd ? + =
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